Next Generation Internet High-Speed Switches and Routers

Shared memory architecture for packet switches was normally thought to be unsuitable for building high performance switches/routers. The main reason lies in their perceived poor scalability. In particular, shared memory architectures are typically used to build output-queued switches which are regarded as the best candidate to achieve optimal delay-throughput performance. The current trend in router/switch design in both industry and academia favors crossbar-based architectures with VOQ techniques because they provide a scalable solution. Although shared memory architectures seem to have the obvious scalability disadvantage, crossbar-based architectures have their own intrinsic limitations, such as complex scheduling algorithms and higher bandwidth allocation compared with shared memory architectures of the same capacity. In this survey, we investigate the problem of shared memory design in detail and try to find alternatives to solve the scalability bottleneck. In the end, we show that combining the crossbar and distributed shared memory architecture is the most promising method for building scalable high performance switches/routers that can provide quality-of-service support.